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ASTRO (RFSoC SOM)

Powered by Gen3 AMD RFSoC, ASTRO is our standalone Radio Frequency System On Chip (RFSoC) designed for highly adaptable RF processing.

ASTRO is designed integrate onto custom carrier boards, including ASTRO Nova and ASTRO 3U VPX. Its small form factor reduces the complexity of the base board carrier design and is focused towards multi-channel and beamforming applications for your tactical advantage.

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  • The small form factor of the module is designed to be as flexible as possible. This approach allows the module to be installed into a small form factor design, the designer is required to consider the additional thermal requirements that are supported via interface documentation

    It is possible to connect the module to a VITA 57.4 mating connector, for example on an FPGA development board, further mechanical considerations required to break out the RF connector.

    For full details on the following, please download our datasheet from the top of this page:

    • Clocking Architecture 
    • System Diagram
    • System Clocking Diagram
    • Mechanical Outline
    • Integration
      • Case study overview of integrating ASTRO into a custom carrier case
      • 64 TX/RX Radar Digital Beamformer – Multi-ASTRO synchronisation
    • Firmware & Software
      • Supported SDKs
      • API / Driver Support
      • Remote Management
    • Platform Interface GUIs
    • IP Core Modules
    • Support for Open Source
    FPGA & SOCXilinx Zync UltraScale+ Gen 3
    XCZU48DR-2FFVG1517I (Variants and speed grade options)
    Quad Core (4x) ARM® Cortex™-A53 MPCore™ – 1.3 GHz
    Dual Core (2x) ARM® Cortex™-R5F MPCore™ – 533 MHz
    8x 14 bit 5 GSPS RF-ADC
    8x 14 bit 10 GSPS RF-DAC
    1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x,
    40x Decimation / Interpolation
    8x SD-FEC cores (ZU48 only)
    2x PCIe Gen3 x16 / Gen4 x8
    Power RequirementsPower Supply: +12 V Main power, +3.3V Control
    Power consumption: Typical 15-30 W, up to 75 W (dependent on configuration)
    Thermal Design: FPGA heatsinking required; thermal monitoring onboard temperature sensors
    EnvironmentalTemperature: Operational: -40 to +70 °C; Storage: -40 to +85 °C
    Relative humidity: 0 to 95 %, non-condensing
    Memory and StorageDDR4 SDRAM:
    PS – 32 Gbit (8 GB)
    LS – 32 Gbit (8 GB)
    Non-Volatile Storage
    eMMC – 16 GByte (Options up to 64 GB)
    QSPI – 4 GBit (Dual 2 Gbit)
    Clocking ArchitectureHighly integrated with onboard VCXO (see system diagram within datasheet)
    Digitial Interface Key FunctionsConnector: ASP-188588-01 (SEAM-40-02.0-14-A)
    VITA 57.4 (FMC+) Electrical
    SD Card Interface, boot mode configuration
    UART, JTAG
    High speed 28 Gbps GTY and GTR interfaces
    System and RF clocks configuration interface
    Health monitor via onboard controller
    RF Interface Key FunctionsConnector: SEAM-20-02.0-L-06
    8 DAC, 8 ADC differential pairs
    DAC, ADC Sample Clocks
    SYSREF, SYNC
    I2C and GPIO
    Mechanical Dimensions: 94 mm x 69 mm x 13.5 mm
    Mass: 110 g
    Software & FirmwareSoftware and firmware support package
    GUI software for ASTRO control and configuration
    • Model: 020-0062
    • Description: FMC – 8CH A/D & D/A Zync Ultrascale+ RFSoC Gen 3
    • Selection: 020-0062-[A]-[B]-[C]-[D]-[E]-[F]-[G]-[H]
    BuildCodeDescription / Part #
    Standard Part Number Standard020-0062-A1-B2-C1-E2-F1-G1-H1
    FPGAAA1 = ZU48*
    FPGA Speed Grade (See AMD Datasheet)BB1 = -1
    B2 = -1L*
    B3 = -2
    B4 = -2L
    FPGA TemperatureCC1 = I (Industrial)*
    C2 = E (Extended)
    eMMCEE1 = 8 GB
    E2 = 16 GB*
    E3 = 32 GB
    E4 = 64GB
    Internal VCXOFF1 = 122.88MHz*
    F2 = 100MHz
    Conformal CoatingGG1 = Non
    G2 = Acrylic
    G3 = Polyurethane
    Custom OptionsHH1 = None

The small form factor of the module is designed to be as flexible as possible. This approach allows the module to be installed into a small form factor design, the designer is required to consider the additional thermal requirements that are supported via interface documentation

It is possible to connect the module to a VITA 57.4 mating connector, for example on an FPGA development board, further mechanical considerations required to break out the RF connector.

For full details on the following, please download our datasheet from the top of this page:

  • Clocking Architecture 
  • System Diagram
  • System Clocking Diagram
  • Mechanical Outline
  • Integration
    • Case study overview of integrating ASTRO into a custom carrier case
    • 64 TX/RX Radar Digital Beamformer – Multi-ASTRO synchronisation
  • Firmware & Software
    • Supported SDKs
    • API / Driver Support
    • Remote Management
  • Platform Interface GUIs
  • IP Core Modules
  • Support for Open Source
FPGA & SOCXilinx Zync UltraScale+ Gen 3
XCZU48DR-2FFVG1517I (Variants and speed grade options)
Quad Core (4x) ARM® Cortex™-A53 MPCore™ – 1.3 GHz
Dual Core (2x) ARM® Cortex™-R5F MPCore™ – 533 MHz
8x 14 bit 5 GSPS RF-ADC
8x 14 bit 10 GSPS RF-DAC
1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x,
40x Decimation / Interpolation
8x SD-FEC cores (ZU48 only)
2x PCIe Gen3 x16 / Gen4 x8
Power RequirementsPower Supply: +12 V Main power, +3.3V Control
Power consumption: Typical 15-30 W, up to 75 W (dependent on configuration)
Thermal Design: FPGA heatsinking required; thermal monitoring onboard temperature sensors
EnvironmentalTemperature: Operational: -40 to +70 °C; Storage: -40 to +85 °C
Relative humidity: 0 to 95 %, non-condensing
Memory and StorageDDR4 SDRAM:
PS – 32 Gbit (8 GB)
LS – 32 Gbit (8 GB)
Non-Volatile Storage
eMMC – 16 GByte (Options up to 64 GB)
QSPI – 4 GBit (Dual 2 Gbit)
Clocking ArchitectureHighly integrated with onboard VCXO (see system diagram within datasheet)
Digitial Interface Key FunctionsConnector: ASP-188588-01 (SEAM-40-02.0-14-A)
VITA 57.4 (FMC+) Electrical
SD Card Interface, boot mode configuration
UART, JTAG
High speed 28 Gbps GTY and GTR interfaces
System and RF clocks configuration interface
Health monitor via onboard controller
RF Interface Key FunctionsConnector: SEAM-20-02.0-L-06
8 DAC, 8 ADC differential pairs
DAC, ADC Sample Clocks
SYSREF, SYNC
I2C and GPIO
Mechanical Dimensions: 94 mm x 69 mm x 13.5 mm
Mass: 110 g
Software & FirmwareSoftware and firmware support package
GUI software for ASTRO control and configuration
  • Model: 020-0062
  • Description: FMC – 8CH A/D & D/A Zync Ultrascale+ RFSoC Gen 3
  • Selection: 020-0062-[A]-[B]-[C]-[D]-[E]-[F]-[G]-[H]
BuildCodeDescription / Part #
Standard Part Number Standard020-0062-A1-B2-C1-E2-F1-G1-H1
FPGAAA1 = ZU48*
FPGA Speed Grade (See AMD Datasheet)BB1 = -1
B2 = -1L*
B3 = -2
B4 = -2L
FPGA TemperatureCC1 = I (Industrial)*
C2 = E (Extended)
eMMCEE1 = 8 GB
E2 = 16 GB*
E3 = 32 GB
E4 = 64GB
Internal VCXOFF1 = 122.88MHz*
F2 = 100MHz
Conformal CoatingGG1 = Non
G2 = Acrylic
G3 = Polyurethane
Custom OptionsHH1 = None
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